1. Field of the Invention
The present invention relates to nonvolatile memory (NVM) cell design.
2. Description of the Related Art
The use of solid state NVM devices has increased as more systems and products incorporate increasing numbers of programmable functions and features. Typical NVM cells, such as those used in erasable programmable read only memory (EPROM) devices, typically use two components for each cell: a transistor and a capacitor. In a classical stacked gate cell, a second polysilicon layer is used to create the capacitor. Alternatively, a floating gate capacitor can also be used. Such designs use the transistor in both programming and reading modes of operation, while erasing is done through the transistor or through the capacitor, and coupling to the capacitor determines the operating voltages.
While such a design provides for a compact cell size, the requirement that the transistor and capacitor both be used for multiple functions (e.g., programming, reading, erasing and controlling) prevents such design from being optimized for each function individually.